1. Field of Invention
The present invention relates to integrated circuit, and more particularly to a kind of phase delay line.
2. Description of Related Arts
The multi-phase clock signals with the same frequency produced by the phase delay line are widely used for data acquisition. The conventional delay line mainly includes a plurality of RC delay units connected in series. The process ununiformity causes the mismatch between R and C, which results in the different delays of different phase delay units. Therefore, it is impossible to increase or decrease the phase numbers by inserting or taking off delay unit.